Pulse synchronizer In progress
A one-cycle pulse carried into another clock domain. A toggle flop makes it a level, two flops carry it across, and a flop and an XOR make it a pulse again.
rtl
A one-cycle pulse carried into another clock domain. A toggle flop makes it a level, two flops carry it across, and a flop and an XOR make it a pulse again.
rtl
One rising edge of an input produces exactly one clock period of output. The flip-flop that remembers the last cycle, and the gate that compares.