Gray code counter In progress
A 3-bit binary count with its Gray code loaded beside it at the same edge, and why one bit per step, the wrap included, lets a count cross clock domains.
See RTL run
Live circuits and state machines, a waveform on the same time axis, and the SystemVerilog that produces them. Written by an RTL design engineer who would rather show you the edge than describe it.
Run plays this scenario from the start; driving an input continues from here.
A circuit that runs: a schematic and its waveform on one time axis. Inputs: d. Outputs: q. clk runs at 8 ticks a period. It is built from 1 D flip-flop. The waveform shows clk, d, q.
Circuits
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rtl
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Linear-feedback shift register (LFSR) In progress
Four flip-flops and one XOR that step through every nonzero 4-bit value, fifteen in all. The taps, the seed a reset must load, and the value it cannot leave.
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Pulse synchronizer In progress
A one-cycle pulse carried into another clock domain. A toggle flop makes it a level, two flops carry it across, and a flop and an XOR make it a pulse again.
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D flip-flop In progress
A D flip-flop takes d at each rising edge of the clock and holds it until the next. The always_ff that describes it, an enable, and an asynchronous reset.
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Reset synchronizer In progress
Two flip-flops that assert a reset at once and release it only just after a clock edge. Why the release has to be synchronous, shown on a ring it can break.
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Shift register In progress
Four flip-flops in a row that take one bit per edge and hold the last four side by side. Serial in, parallel out, and what the order of four lines decides.
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Sequence detector for 1011 In progress
A Moore state machine that finds 1011 in a serial bit stream, overlaps included. Five states, ten arrows, and the one state that reports a match.
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Traffic-light controller In progress
A four-state Moore machine for a junction, where a timer and the side road's queue decide when green changes hands. Holding, bus outputs, a synchronous reset.
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UART receiver state machine In progress
The control state machine of a UART receiver, with its counters outside it. Priorities, Mealy outputs on arrows, a framing error and a false start.
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4-bit decade counter In progress
A counter drawn as one box, and a count that leaves it as a bus. What a block hides, and how four bits travel on one wire and one waveform row.
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Rising-edge detector In progress
One rising edge of an input produces exactly one clock period of output. The flip-flop that remembers the last cycle, and the gate that compares.
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Static-1 hazard In progress
An output that should have stayed high dips for two ticks, because two paths through the logic are not the same length. The consensus term covers the gap.
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Two-flop synchronizer In progress
One asynchronous input into a single flip-flop and into two, side by side. What metastability looks like, and what the second flop actually buys.
Tools
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Boolean simplifier: Karnaugh map solver, minimal SOP and POS
- Takes
- an expression, a minterm list or a Karnaugh map
- Gives
- the minimal SOP and POS, the map, their SystemVerilog and a two-level circuit where one fits
- Limit
- 6 variables
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Float format explorer: IEEE 754, bfloat16, FP8
- Takes
- a decimal or a bit pattern
- Gives
- the encoding, the exact value, its neighbours and the error
- Limit
- up to 64 bits; round to nearest, ties to even, only
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FSM viewer: Verilog and SystemVerilog code to state diagram
- Takes
- a state machine in Verilog or SystemVerilog
- Gives
- a live state diagram, its waveform, linked to your code
- Limit
- 64 KiB and 32 states read; long names draw fewer
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Sequence detector generator: Moore and Mealy FSMs in SystemVerilog
- Takes
- a bit pattern of 1 to 6 bits
- Gives
- a live state machine, its waveform and its SystemVerilog
- Limit
- 6 bits