Tools
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Boolean simplifier: Karnaugh map solver, minimal SOP and POS
- Takes
- an expression, a minterm list or a Karnaugh map
- Gives
- the minimal SOP and POS, the map, their SystemVerilog and a two-level circuit where one fits
- Limit
- 6 variables
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Float format explorer: IEEE 754, bfloat16, FP8
- Takes
- a decimal or a bit pattern
- Gives
- the encoding, the exact value, its neighbours and the error
- Limit
- up to 64 bits; round to nearest, ties to even, only
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FSM viewer: Verilog and SystemVerilog code to state diagram
- Takes
- a state machine in Verilog or SystemVerilog
- Gives
- a live state diagram, its waveform, linked to your code
- Limit
- 64 KiB and 32 states read; long names draw fewer
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Sequence detector generator: Moore and Mealy FSMs in SystemVerilog
- Takes
- a bit pattern of 1 to 6 bits
- Gives
- a live state machine, its waveform and its SystemVerilog
- Limit
- 6 bits