D flip-flop

How it works, edge by edge

Follow the q row. The rising edges of clk are at ticks 4, 12, 20 and 28, and q changes at edges and nowhere else. It has a value even before the first: rst_n is low from tick 0, and an asynchronous reset gives q its 0 at once, without waiting for an edge. The reset is released at tick 2, between edges, and the release by itself changes nothing.

At the first edge q becomes 1: d has been 1 since tick 1. At the second edge q becomes 0, because d fell at tick 7. In both, the value q takes is the one d held just before the edge.

Between the second and the third edge d rises at tick 14 and falls again at 17. No edge falls inside that pulse, so at tick 20 d is 0 again and q stays 0. A flip-flop samples; it does not follow.

d rises at tick 21, and en falls at 22. With en at 1 the multiplexer in front of the flop passes d; at 0 it passes q back into the flop's own input. So at tick 28 the edge arrives as usual and loads what q already holds: q stays 0 although d is 1. The clock never stopped.

On the edge drives d the way the output of another flip-flop on the same clock changes in a simulation without delays: in the tick of each rising edge. d rises at tick 4 and q does not, because the edge takes the 0 that d held just before it. q rises at 12 instead, one period later, and from then on the q row is the d row shifted right by a clock period.

Reset pulls rst_n low at tick 9, in the middle of a period. q falls in the same tick, with no edge. The edge at tick 12 changes nothing, because the reset holds q at 0 whatever d is. rst_n rises again at 17, between edges, and q stays 0 until the edge at 20 loads the 1 on d.

The code

// A D flip-flop with an enable: at each rising edge of clk it takes d if en is
// high and keeps what it has if not. Between edges nothing on d reaches q.
//
// Reset style for this module: asynchronous, active low. One style per page,
// stated up front, so nothing on the page has to be read twice.
module d_flip_flop (
    input  logic clk,
    input  logic rst_n,
    input  logic en,
    input  logic d,
    output logic q
);

  // rst_n is in the sensitivity list, so the reset acts the moment it falls;
  // its release is seen only by the next rising edge of clk.
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      q <= 1'b0;
    end else if (en) begin
      // No else: with en low the flop keeps q, which is what a flop does.
      q <= d;
    end
  end

endmodule

The reset style is stated at the top of the file and used once: asynchronous, active low. The always_ff block is the flip-flop, and rst_n in its sensitivity list is what makes the reset act the moment it falls rather than at the next edge.

The multiplexer in the drawing is the else if (en). When en is 0 no branch assigns q, and an always_ff that assigns nothing at an edge keeps q — which is exactly the multiplexer's 0 input feeding q back. There is no else q <= q; because none is needed. Synthesis folds the multiplexer back into the flip-flop: the result below is a flop with its enable built in.

Synthesis result

Yosys's generic synthesis turns d_flip_flop.sv into 1 cell, 1 of them a flip-flop. The cells are Yosys's own gate library, not an FPGA's or a standard-cell library's: the count measures the logic, not the area of any chip.

Lint by Verilator 5.052, the testbench by Icarus Verilog 13.0, synthesis by Yosys 0.66.

Icarus replayed this page's three scenarios on this code, and all 510 values the waveform draws match.

Pitfalls

A blocking assignment in always_ff. Write q = d; instead of q <= d; and this one flop does not change: Yosys builds the same netlist from both. What breaks is the simulation of everything else that reads q at that edge. With =, q takes its new value in the same step, and another always_ff reading q sees the new value or the old one depending on which block the simulator happens to run first. On the edge shows what every reader of a flop must see: the value from before the edge, which is what <= guarantees. Verilator's -Wall and Verible both flag = in always_ff. On a chain of flops the order of the lines then decides what is built, as the shift register shows.

An enable written as an incomplete if, in the wrong block. Here if (en) with no else is the enable, because always_ff keeps q when nothing assigns it. Move the choice into combinational logic — if (en) d_next = d; in an always_comb feeding the flop — and when en is 0 nothing keeps d_next but a latch: a store that is open while en is high, sitting in front of the flop. Verilator's -Wall warns of it, and Yosys refuses to synthesize an always_comb that needs one; Verible, which lints this site's snippets, says nothing. Written as always @*, the same lines build the latch.

A reset released near an edge. Reset releases rst_n between edges, and the edge after it loads d. Where a release comes from decides whether that is safe. A release launched by a flop on the same clock changes just after an edge, like any flop's output, and timing analysis checks it against the edges on either side of it, as it checks the setup and hold of any other path.

A release from a pin or from another clock domain can land on the edge itself. In simulation the answer then depends on how the release is driven. Written as a flop's own output with <=, the release holds the flop in reset at that edge. Written with =, it races the edge: whichever block the simulator runs first wins, and two simulators can disagree on the same code. In silicon a release that close to an edge breaks the flop's recovery or removal time and can leave it metastable, which this engine does not check. Keeping the release away from the edge is what a reset synchronizer is for.

Reading the waveform one edge early. In On the edge, d and the edge change in the same tick, and it is tempting to read q as changing with them. It does not: the edge takes what d held before it, and q shows that until the next edge. Read a flop's output after its edge, and its input just before.