Linear-feedback shift register (LFSR) In progress
Four flip-flops and one XOR that step through every nonzero 4-bit value, fifteen in all. The taps, the seed a reset must load, and the value it cannot leave.
Tagged flip-flop
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Pulse synchronizer In progress
A one-cycle pulse carried into another clock domain. A toggle flop makes it a level, two flops carry it across, and a flop and an XOR make it a pulse again.
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D flip-flop In progress
A D flip-flop takes d at each rising edge of the clock and holds it until the next. The always_ff that describes it, an enable, and an asynchronous reset.
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Reset synchronizer In progress
Two flip-flops that assert a reset at once and release it only just after a clock edge. Why the release has to be synchronous, shown on a ring it can break.
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Shift register In progress
Four flip-flops in a row that take one bit per edge and hold the last four side by side. Serial in, parallel out, and what the order of four lines decides.
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Rising-edge detector In progress
One rising edge of an input produces exactly one clock period of output. The flip-flop that remembers the last cycle, and the gate that compares.
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Two-flop synchronizer In progress
One asynchronous input into a single flip-flop and into two, side by side. What metastability looks like, and what the second flop actually buys.